In dynamic semiconductor memory storage devices it is essential that the storage node capacitor retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continue to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required storage capabilities is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node capacitance in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two layers of conductive material, such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer with a dielectric layer sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining high dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A paper submitted by Reza Moazzami et al., entitled "A Ferroelectric DRAM Cell for High-Density NVRAM's," IEEE ELECTRONIC DEVICE LETTERS, VOL. 11, NO. 10, OCTOBER 1990, pp. 454-456, herein incorporated by reference, discusses the use of a PZT ferroelectric material as a cell dielectric in a planar capacitor.
As discussed on pp. 455 in section B. DRAM Mode, a PZT ferroelectric material has been used as the storage cell's dielectric film. As stated and shown in FIG. 3a, pp. 455, very little degradation was observed in the small-signal capacitance after 10.sup.10 read/write cycles.
The PZT ferroelectric material has a high dielectric constant very favorable for use as a storage cell dielectric, but as discussed in this article PZT has only been used experimentally in planar storage capacitors. It is also a much electrically leakier film than nitride films that are in current use and must be deposited much thicker to reduce this undesirable current leakage. The selection of electrode materials now becomes critical when using a PZT cell dielectric. Reza et al. reports the use of platinum metal electrodes which are incompatible with silicon device manufacturing.
Using a high dielectric constant material as the cell dielectric presents a cell leakage problem that must be taken into consideration that is different from a conventional storage capacitor. As illustrated in FIG. 1a, a conventional storage cell using a thin dielectric, such as nitride, is depicted. I.sub.1 represents leakage current between a capacitor's top and bottom cell plates (or top cell plate and storage node cell plate). I.sub.2 represents leakage current between adjacent storage node cell plates. A worst case scenario for cell to cell leakage would be 0 volts on storage node 1 and Vcc volts on adjacent storage node 2 with Vcc/2 on common top plate 3. A typical planar cell dielectric is 0.01 microns thick while the storage node to storage node spacing is 1.0 microns. The conventional storage cell present leakage current I.sub.1 as the dominant leakage that one must be concerned with as I.sub.1 &gt;&gt;I.sub.2 as the capacitor's top and bottom cell plates are closer to one another than are adjacent storage node cell plates.
Referring now to FIG. 1b, a cell (later to be developed in the present invention) using a high dielectric constant material for its cell dielectric must contain a much thicker layer of dielectric than one having a nitride cell dielectric, but due to its high dielectric breakdown characteristics at this increased thickness, leakage current I.sub.1 becomes very small. At the same time however, if the surface area of the storage node cell plate is to be maximized, the spacing of adjacent storage node cell plates becomes less than the spacing between the two cell plates of the capacitor. However, even if the storage node to storage node distance remains fixed at 1.0 microns, there is 2.times. greater potential difference between adjacent storage nodes as compared to storage node to top plate. So in the case of the present invention represented in FIG. 1b, I.sub.2 &gt;&gt;I.sub.1 and a process must be developed (which is described in the following text) to eliminate this cell to cell leakage, I.sub.2 while maintaining high cell capacitance and close cell to cell spacing.
The present invention addresses both leakage current issues by fabricating a storage cell using a high dielectric constant material combined with a conventional dielectric in a preferred embodiment or alternatively, a storage cell using only a high dielectric constant material in a second embodiment. Both embodiments modify an existing stacked capacitor fabrication process to construct a three-dimensional stacked capacitor cell that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions.